1. Field of the Invention
The present invention relates to a method of reading a memory device in a page mode and a row decoder control circuit using the same, and more particularly, to a method of reading a memory device in a page mode wherein word lines are enabled by application of a row address and the word lines are disabled after a lapse of a certain time period as much as data of the first cell node is restored, and a row decoder control circuit using the same.
2. Discussion of Related Art
A page mode is one capable of eliminating a row address delay when access is made to the same rows. A set of bit cells within a single row is referred to as a page of the data.
A conventional method of reading a memory device in the page mode will now be described.
FIG. 1 is a circuit diagram illustrating a conventional structure in which a DRAM cell and a bit line sense amplifier are interconnected. NMOS transistors N1, N2:10 having gates each applied with a BISH signal serve as a switching for connecting to upper side cells. A sense amplifier 20 includes PMOS transistors P1, P2 for pulling up a bit line BL to a HIGH level and NMOS transistors N3, N4 for pulling down the bit line BL to a LOW level. Meanwhile, a bit line equalizing circuit 30 includes NMOS transistors N7, N8 and N9 for initializing the bit line BL and each node of a bit line sense amplifier BLSA using a bit line precharge signal (BLP). NMOS transistors N5, N6 function to transmit the data of the bit line BL to a line LDB by applying a column address (YI). Further, a signal for driving the bit line sense amplifier is applied through lines RTO, SB.
FIG. 2 is a timing diagram illustrating an operating waveform of the DRAM cell and the bit line sense amplifier according to the prior art. Referring to FIG. 2, at the initial state, while the bit line BL is initialized by bit line precharge voltages (VBLP, Vcore/2) in a period (1), the voltages of the cell node CN and the bit line BL are then charge-shared after the word line WL is enabled in a period (2). If the bit line sense amplifier is then enabled after a sufficient time period, the bit line BL is amplified by still higher voltage in a period (3). The signal amplified thus is connected to the local data bus LDB by the column decoder signal (yi) in a period (4). At this time, a local data bus LDB that has been precharged is gradually dropped to a lower voltage by the bit line sense amplifier. In a period (5), the column decoder signal (Yi) is disabled. After a given period of time elapsed, the voltage of the cell node CN is sufficiently restored. In a period (6), the word line WL is disabled. After a lapse of a certain time period, the bit line sense amplifier is disabled. Each of the nodes of the bit line and the bit line sense amplifier is initialized to become a state like the (1) period.
From the above operation, it could be known that the word line WL must be always disabled after the cell node CN is restored as much as a given voltage (Vcore) level, for a stable operation. This is a problem occurring due to the fact that the cell has to be restored again if the read operation is once performed with characteristics of the DRAM cell. In other words, if the word line is once enabled, the word line needs to be disabled after a previous data is again written into the cell.
Meanwhile, in the memory device of the page mode, the data is read while changing only the column address after the word line is enabled. As shown in FIG. 2, the data is read while a column decode signal (Yi) is continuously toggled in a state where the word line is enabled.
FIG. 3 shows a waveform of a word line control signal in the read operation of the page mode according to the prior art. AN indicates an external address, AP a page address, AX an internal address outputted through the address buffer, BAX(0) a signal outputted from the row decoder in order to drive an 0th word line, and WL0 a signal applied to the 0th word line. Time ((1) in FIG. 3) for disabling a new external address (AN) when it is inputted is always required. FIG. 4 shows a waveform of the word line control signals where the external address is inputted due to the interrupt when the read operation is performed in the page mode. That is, it shows a case where a new external address (AN) is inputted at an early stage. Once the external address (AN) is changed, the column decoder signal (Yi) is disabled to cancel the operation of reading the data in the bit line sense amplifier. For a certain time period, time for the cell node CN to perform the restore operation is needed. The operation can be performed for an external address that has been newly changed after the word line was disabled.
Therefore, in the read operation of the page mode that had been executed before the new external address (AN) was inputted, it is required that the word line WL(0) be disabled and a next word line WL1 be enabled, after the restore operation is executed until the voltage of the cell node CN reaches a stable state by the voltage applied to the bit line. As shown in FIG. 4, therefore, in order to enable a word line corresponding to an input address (AN) that is newly inputted, as much time as ((3) in FIG. 4) is more required. In other words, in order to enable the word line corresponding to the input address (AN) that is newly inputted, as much time as (1)+(2)+(3) is required.
While the voltage applied to the bit line is varied, the cell node CN is changed along the bit line. This is applied to all the cases where a LOW-level voltage or a HIGH-level voltage is stored at the cell node. For this reason, the word line structure in which the word line must be continuously enabled until the external address is changed, has problems that it causes the entire access time to be delayed and increases current consumption.